# Generated by makepkg 7.0.0
# using fakeroot version 1.37.1.2
pkgname = vtr
pkgbase = vtr
xdata = pkgtype=pkg
pkgver = 9.0.0-1.0
pkgdesc = Verilog to Routing -- Open Source CAD Flow for FPGA Research
url = https://verilogtorouting.org
builddate = 1755381258
packager = Andreas Baumann <mail@andreasbaumann.cc>
size = 25723936
arch = pentium4
license = MIT
depend = ctags
depend = tbb
makedepend = cmake
makedepend = wget
